The testing cost for complex system-on-chip (SoC) integrated circuits (ICs) is growing fast, especially in the case of devices including non-volatile memory portions. To reduce the test cost of complex SoC ICs, such as an SoC including an embedded flash memory, three different possibilities can be chosen: reduce the embedded flash intrinsic test time; insert a partial/full BIST (built-in self test) approach; and increase the test parallelism by probing a small subset of pins. The first two approaches can have a big impact on the device area, so the third approach is preferably the preferred one.
Using a standard software tool and including a compressor/decompressor architecture, it is possible to perform tests with a plurality of scan chains. More particularly, a compression architecture generally comprises a decompressor receiving test input bit streams from a set of pins to load the plurality of scan chains. The SoC is tested with the scan chains and produces corresponding test output bit streams. A compressor receives the test output bit streams, compress it in a scan output that is compared to a predicted pattern to determine whether an error occurred during testing.
Using the architecture described above it is possible to perform tests on different levels of the device. For example, the tests include tests at the electrical wafer level executed for each single wafer, and tests at the package level executed as a final step before the delivery of the package. In this compression architecture the same set of pins and the same plurality of scan chains is used to execute the tests on a package level and on a wafer level.
A disadvantage of this architecture is that the parallelism of the tests at the wafer level is very limited because a large number of bits involved in the package level test are used for the wafer level test. Two specific constraints should be taken in consideration: the test time and the test parallelism.
More particularly, since the entire pins of the package are typically probed at the package level test, it is important to reduce the test time during a package level test. At the same time, since a plurality of devices on the same wafer may be tested during the electrical wafer test, it is important to improve the test parallelism in the electrical wafer test.
With an architecture comprising a specific configuration of pins and of scan chains it is only possible to obtain a compromise between the test parallelism and the test time, or to advantage one constraint to the detriment of the other.
A specific design tool available in standard software tool and known as a design for testability compiler that allows implementation of different architectures to improve the flexibility of the design for testability structures is inserted in the SoC for specific test requirements.
A known available approach is the multi-mode architecture that allows the implementation of multiple scan chains configurations (or modes). It is common in this environment to have two configurations: a standard scan chain mode and a burn-in scan chain mode.
In the standard scan chain mode the number of internal scan chains depends on the maximum number of available I/O pins at the top level and on the test equipment constraints. These features are schematically shown in FIG. 1 which provides an improved architecture with N scan chains.
In the burn-in scan chain mode all internal scan chains are serially connected in a single long scan chain by a multiplexer for allowing a higher parallelism in the testing step since more devices can be tested in parallel. FIG. 1 also shows the alternative approach wherein a multiplexer shown by the dotted line connects all the chains in a single long chain.
A scan architecture may be optionally available for allowing insertion of a decompression multiplexer logic block between fewer external scan chain inputs and the internal scan chain inputs, along with a compression XOR logic based block between the internal scan chain outputs and fewer external scan chain outputs.
This further available approach is schematically shown in FIG. 2 wherein the main hardware portions are shown. The decompression multiplexer connects several internal scan chain inputs to a single external scan chain input for allowing a higher degree of parallelism in the testing step, quantified in a compression factor parameter.
These known approaches still present some limitations, mainly when there is a need to perform testing steps requiring different degrees of parallelism. More specifically, the increasing complexity of the current system-on-chip (SoC) integrated circuits (ICs), especially but not only those including embedded Flash memories, along with the increasingly stringent quality requirements, gives rise to a consequential increase of the overall test cost which does not support the current trend to reduce as much as possible the device test time/cost.
The problem is particularly relevant when the inserted deign for testability structure needs to be used both in testing steps where a high degree of parallelism is required, for example in electronic wafer level testing, and in testing steps where a low time test is required, for example in the package level test.